// dual port distributed ram (LUT ram)
// implement with Xilinx primitive xpm_memory_dpdistram
// refered from nontrivial-mips project
module dpdistram #(
  parameter WIDTH = 32,
  parameter DEPTH      = 1024,
  parameter LATENCY    = 0,
  parameter LATENCY_A  = LATENCY,
  parameter LATENCY_B  = LATENCY
) (
  input  clk,
  input  rst,
  input  wea,
  input  ena,
  input  enb,
  input  [$clog2(DEPTH)-1:0] addra,
  input  [$clog2(DEPTH)-1:0] addrb,
  input  [WIDTH-1:0] dina,
  output [WIDTH-1:0] douta,
  output [WIDTH-1:0] doutb
);

xpm_memory_dpdistram #(
  // Common module parameters
  .MEMORY_SIZE(WIDTH * DEPTH),  // memory size in bit
  .USE_MEM_INIT(0),             // initialize the ram with 0

  // Port A module parameters
  .WRITE_DATA_WIDTH_A(WIDTH),
  .READ_DATA_WIDTH_A(WIDTH),
  .READ_LATENCY_A(LATENCY_A),   // set lantency with 0 to implement lut ram

  // Port B module parameters
  .READ_DATA_WIDTH_B(WIDTH),
  .READ_LATENCY_B(LATENCY_B)    // set lantency with 0 to implement lut ram
) xpm_mem (
  // Port A module ports
  .clka           ( clk   ),
  .rsta           ( rst   ),
  .ena            ( ena   ),
  .regcea         ( 1'b0  ),
  .wea            ( wea   ),
  .addra          ( addra ),
  .dina           ( dina  ),
  .douta          ( douta ),

  // Port B module ports
  .clkb           ( clk   ),
  .rstb           ( rst   ),
  .enb            ( enb   ),
  .regceb         ( 1'b0  ),
  .addrb          ( addrb ),
  .doutb          ( doutb )
);

endmodule